CMOS scaling according to Moore's law has been providing the semiconductor industry with reduced transistor size while offering enhanced performance. However, in order to continue scaling, new channel materials having a high carrier velocity may be desirable.
Field effect transistors (FinFETs) incorporating fin structures having III-V compound semiconductors as channel material are considered to be attractive candidates for high-performance n-type FETs in the semiconductor industry.
Use of III-V substrates for the production of such FinFETs may be a challenging task due to III-V materials lacking thermally and electrically stable native oxides. Therefore, during Shallow Trench Isolation (STI) formation, where a dielectric material (such as SiO2) is deposited to fill trenches made in the III-V substrate, an electrically active and thermally unstable interface can form between the STI and the III-V substrate. Such interface can lead to a high leakage path between gate, source, and/or drain regions of the transistor. In U.S. Patent Application Pub. No 2011/0140229 A1, a method for forming a STI structure is disclosed, where a passivation layer is applied on the surfaces of the shallow trench isolation made in the substrate. The passivation layer restricts free bonding electrons of the substrate material by covalently bonding to them. The substrate material is disclosed to include Ge, SiGe or III-V material. Additionally, the passivation layer is oxidized, thereby forming a bi-layer to form an electrically defect-free interface.
Although the problem of making FETs starting from a III-V substrate can be solved by the use of the passivation layer as disclosed in US 2011/0140229 A1, use of III-V material as the substrate material remains a challenge due to the production of FinFETs on III-V substrates being expensive. Furthermore, it may be difficult to co-integrate of III-V channels and Ge channels, as Ge is a candidate for high-performance p-type FETs.
Therefore, the integration of III-V FinFETs on a Si substrate may be advantageous with respect to cost effectiveness, and may open doors to co-integration of III-V with Ge channels. However, large lattice mismatch between III-V materials and silicon makes it a technological challenge to grow III-V materials on silicon. Such large lattice mismatch between III-V materials and the Si substrate leads to the formation of crystalline defects, such as dislocations, anti-phase boundaries, twins and stacking faults. Presence of these defects are detrimental for device performance.
A technique called Aspect Ratio Trapping (ART) is a way to realize non-silicon channels on a silicon substrate. In this technique, high aspect ratio trenches are created in between shallow trench isolation (STI) structures on silicon substrate. Fins made of III-V compound semiconductors are then formed in these trenches by selective epitaxial growth (SEG). The crystalline defects originating from the lattice mismatch are guided to the STI sidewalls and there trapped, which enable obtaining active regions with a small amount of defects. An aspect ratio greater than 1 is used in order to trap the crystalline defects.
It is a challenge, however, to produce III-V fins using the ART technique. Because ART uses SEG, the precursors used in SEG interact not only with the silicon substrate but also with the STI structures which are SiO2. Such interactions could lead to the formation of defects in the STI structures, and such defects in turn degrade the electrical and structural reliability of the transistor.
Generally, defects formed in STI structures can be of two types. In-diffusion of the doping atoms, which are present in the SEG precursors, into the STI structures leads to the formation of a first type of defects, which are interstitial defects in SiO2. Oxidation of these doping atoms at the surface of the STI structure leads to the formation of a second type of defects, which are oxygen vacancies in SiO2 formed by depleting the oxygen from SiO2.
One of the solutions to cope with the problem of defects is envisaged by improving the epitaxial quality of the ART process. However, this is a challenging task for the ART process as the ART technique is applied to grow non-Si semiconductor on Si substrate, where large lattice mismatch exists between the Si substrate and the non-Si semiconductor. Thus, crystalline defects may not be avoided, at least at the bottom of grown non-Si crystals.
Another alternative solution to cope with the problem of defects is to change the type of the doping present in the precursors. However, this can only change the extent of defectivity problem, but does not solve it effectively.
In, Al, Ga, P, As, Mg and Zn are the typical alternatives of species contained in the precursors.
Formation energies of the reactions, in which III-V atoms and doping atoms in the precursors move into the SiO2, decreases during the course of the growth process as the precursors begin losing their organic ligands. This means that the thermodynamic driving force for the in-diffusion of III-V atoms and doping atoms increases.
Reaction enthalpies for the formation of native (sub) oxides as a result of the reaction of precursors with the oxygen of SiO2 decreases during the course of the growth process. Formation of such native (sub) oxides is also not generally desired.
There is, therefore, a desire in the art to produce III-V fin structures using a method such that degradation of the device performance is avoided or reduced